1) Field of the Invention
The present invention relates to a semiconductor multilayer wiring board having a semiconductor multilayer wiring which has a lower wiring layer formed on a semiconductor substrate, and an upper wiring layer formed on the lower wiring layer via a interlayer insulating layer The lower wiring layer and the upper wiring layer are connected to each other via a via-wiring vertically penetrating the interlayer insulating layer The present invention also relates to a method of forming such a semiconductor multilayer wiring board. In more detail, the present invention relates to a semiconductor multilayer wiring board in which the via-wiring and the lower and upper wiring layers are formed by a simple dual damascene process, and all layers from the interlayer insulating layer to the wiring layers are formed by a wet method, and relates to a method of forming such a semiconductor multilayer wiring board.
2) Description of the Related Art
As well known, a basic wiring structure in a semiconductor integrated circuit has a lower wiring layer directly or indirectly formed on a semiconductor substrate and an upper wiring layer formed on the lower wiring layer via an interlayer insulating layer, and the lower wiring layer and the upper wiring layer are connected to each other via a via-wiring which penetrates the interlayer insulating layer. With such a wiring structure being made plural and multilayered, a multilayer wiring structure of a semiconductor integrated circuit is formed.
Conventionally, this wiring structure has been achieved by repetition of laminating procedures of layers such as the conductive layers and the interlayer insulating layer on the semiconductor substrate and etching procedures for patterning of these layers. Such a method of sequentially forming a multilayered wiring by repetition of lamination and etching requires a large number of steps, which tends to raise manufacturing cost. Therefore, at present, an inlaying scheme generally called a damascene process is adopted. In the damascene process, a via hole or a wiring ditch called a trench for forming a via-wiring and an upper wiring layer is formed in advance on an interlayer insulating layer, and then a conductive material is embedded in that space. In the damascene process, a process of simultaneously forming a via-wiring and an upper wiring layer is particularly called a dual damascene process. Adopting this damascene process makes it possible to use copper, which used to be unavailable as a conductive material. That is, although copper is a suitable material as a conductive material for fine wiring because copper has an excellent electromigration resistance compared with aluminum, copper used to be unavailable in the conventional multilayer-wiring sequential forming method due to difficulty in etching. By using the damascene process, however, copper can be eventually used as a conductive material.
A basic procedure of the damascene process will be described with reference to FIGS. 1A to 1D and 2E to 2H.
First, as shown in FIG. 1A, on a substrate 1, an interlayer insulating layer 2 is formed by a CVD method, a spin coating method, or the like. The material constituting this interlayer insulating layer 2 may usually be a SiO2 coating which may be formed by a spin-on-glass (SOG) scheme, a CVD scheme, or the like. On this interlayer insulating layer 2, a resist film 3 is formed and patterned. With this patterned resist film 3 as a mask, the interlayer insulating layer 2 is selectively etched, and then the resist film 3 is removed, thereby forming a wiring ditch (trench) 4 as shown in FIG. 1B. If necessary, on a surface of the interlayer insulating layer 2 with the wiring trench 4 formed thereon, an adhesion layer (not shown), such as a metal-tantalum thin film, is subsequently formed. On the adhesion layer, a barrier metal is then deposited, thereby forming a barrier metal film 5 on the inner surface of the wiring trench 4 for preventing copper to be embedded in the wiring trench 4 from being diffused into the interlayer insulating layer 2. If necessary, a copper seed layer (not shown) is then formed as shown in FIG. 1C. Then, copper is embedded in the wiring trench 4 by electrolytic plating or the like, to form a lower wiring layer 6.
Subsequently, the copper adhered at this time on the surface of the interlayer insulating layer 2 and the remaining barrier metal are removed by chemical polishing (CMP) to planarize the surface of the interlayer insulating layer 2. Then, on that surface, a capping layer 7 is formed. Then, a first low-dielectric layer 8, a first etching-stopper film 9, a second low-dielectric layer 10, and a second etching-stopper film 11 are sequentially laminated. Subsequently, on the second etching-stopper film 11, a resist mask 12 having a pattern for forming a via hole is formed. Subsequently, as shown in FIG. 1D, etching is performed with the resist mask 12 to form a via hole 13 penetrating the second etching-stopper film 11, the second dielectric layer 10, the first etching-stopper film 9, the first low-dielectric layer 8, and the capping layer 7 and reaching the surface of the lower wiring layer 6. Subsequently, as shown in FIG. 2E, the via hole 13 is filled with an embedment material 14, such as a photoresist material. Being etched back, as shown in FIG. 2F, the embedment material 14 is left for a predetermined thickness at the bottom of the via hole 13. Furthermore, on the second etching-stopper film 11, a resist mask 15 having a pattern for forming a trench is formed. By using this resist mask 15, as shown in FIG. 2G, the second etching-stopper film 11 and the second low-dielectric layer 10 are etched to form a trench 16, and simultaneously the embedment material 14 remaining at the bottom of the via hole 13 is removed. If necessary, on the inner surfaces of the via hole 13 and the trench 16, an adhesion layer (not shown), such as a metal-tantalum thin film, is then formed. Subsequently, on this adhesion layer, a barrier metal film (copper-diffusion-preventive film) 17 is formed. If necessary, a copper seed layer (not shown) is then formed on the via hole 13 and the trench 16. Then copper is embedded to form a via-wiring 18 and an upper wiring layer 19, as shown in FIG. 2H. Then, at least on the upper wiring layer 19, a capping layer 20 is formed if necessary. With the process mentioned above, a multilayer wiring structure is achieved in which the lower wiring layer 6 and the upper wiring layer 19 are electrically connected to each other via the via-wiring 18.
In the multilayer wiring structure, as described above, the wiring layers 6 and 19 and the via-wiring 18 are made of copper (Cu). With Cu in each wiring layer being diffused to the interlayer insulating layers 2, 8, and 10, the low dielectric property of the low-dielectric material forming the interlayer insulating layers is impaired, thereby causing an insulation defect. For preventing this problem, it is necessary to place anti-diffusion layers, such as the barrier metal layers 5 and 17 and the capping layers 7 and 20, each between a wiring layer and its surrounding interlayer insulating layer, for preventing Cu from diffusing into the interlayer insulating layers. Conventionally, anti-diffusion films made of TaN, TiN or the like formed by a spattering method have been mainly used. When the wiring layer 19 is formed on the anti-diffusion layer 17 by electroplating, particularly copper electroplating as shown in FIG. 3 which is an enlarged view of main portions of FIGS. 2E to 2H, a Cu seed layer or the like serving as a conductive layer 21 must additionally be provided since the anti-diffusion layer 17 made of TaN, TiN, or the like is relatively low in conductivity.
In the first place, a main reason for adopting the dual damascene process to achieve such a multilayer wiring structure is that a cost reduction by applying such a simplified wet process is considered as being advantageous. Therefore, employment of spattering as described above which is a dry process upon making an anti-diffusion film and conductive layers is obviously not the best procedure.
As alternatives to this method, in recent years, a method of forming a semiconductor multilayer wiring board (a method of manufacturing a VLSI wiring board) has been disclosed in Japanese Patent Laid-Open Publication No. 2003-51538 (hereinafter referred to as “patent document”) in which an anti-diffusion layer as well as a wiring layer and a capping layer can be all formed by a simple wet process with excellent adhesiveness. Also disclosed therein is a semiconductor multilayer wiring board (a VLSI wiring board) in which a capping layer having an excellent adhesiveness, uniformity, and thermal stability is formed by a plated coating.
In these methods of manufacturing a VLSI wiring board, upon manufacturing a VLSI wiring board in which wiring layers are separated by an interlayer insulator made of SiO2 via an anti-diffusion layer, the SiO2 surface forming the interlayer insulating portion is processed by a silane compound, and the surface is further modified to be a catalyst by an aqueous solution containing a palladium compound. Then, an anti-diffusion layer is formed by electroless plating. Subsequently, on this anti-diffusion layer, a wiring layer is formed. In this method, formation of the anti-diffusion layer by electroless plating preferably includes a step of forming a metallic nucleus by neutral or acid electroless plating and then a step of forming an anti-diffusion layer by alkaline electroless plating. The wiring layer may also be directly formed on the anti-diffusion layer by copper electroless plating or copper electroplating.
The methods disclosed in the patent document mentioned above are superior as a conventional method of forming a semiconductor multilayer wiring structure using a dual damascene process. However, if the wiring dimension is extremely finer, even with the use of a copper wiring having a small electrical resistance, an electric-signal speed is prone to decrease under the influence of the dielectric constant of the interlayer insulating film. It is desired to avoid such a delay of the electric-signal speed in the fine wiring.
Such a phenomenon in which the electric signal is delayed can be mitigated by decreasing the dielectric constant of the interlayer insulating film. For example, such an interlayer insulating film can be formed by a CVD method, a coating method such as SOD, etc. In the CVD method, a plasma TEOS (P-TEOS) SiO2 film having a dielectric constant (k value) of approximately 4.1, a SiOF (FSG) film having a dielectric constant of approximately 3.7 to 3.4, a SiOC (carbon doped oxide) film having a dielectric constant of approximately 2.7 to 2.4 are known, for example. Classifying in terms of a coating method, a spin-on-glass (SOG)-based material, and an organic-polymer-based material are known. Known examples of the SOG-based material include a hydrogen silsesquioxane (HSQ) film having a dielectric constant of approximately 2.0 to 3.2, a porous HSQ film, a methylsilsesquioxane (MSQ) film having a dielectric constant of approximately 2.0 to 2.8, a porous MSQ film, and a porous SiO2 film having a dielectric constant of approximately 1.8 to 2.2. Known examples of the organic-polymer-based material include a polyarylene-ether (PAE) film having a dielectric constant of approximately 2.6 to 2.8 film.
Of these materials, when an SOG-based material is used for coating to form an interlayer insulating layer, no expensive apparatus is required, an excellent throughput can be achieved, and most of the process of manufacturing a multilayer wiring substrate can be performed through a wet process. Therefore, the manufacturing process can be simplified and cost reduction can be achieved. As such, according to the coating method using an SOG-based material, an excellent effect can be achieved in which a multilayer wiring substrate can be formed at low cost.
The SOG-based material is mainly a solution formulated by dissolving a hydrolysate of alkoxysilane in an organic solvent.
However, when not only the CVD method and the SOG method described above but also a technology disclosed in the patent document of forming an anti-diffusion film by providing a palladium catalyst to an organic monomolecular film formed on an inner surface of a wiring-layer forming space formed by a dual damascene process is applied to an interlayer insulating layer formed with a silica-based material (silica-based interlayer insulating layer), there may be several problems to be solved. For example, depending on the type of material, the property of the surface of the obtained silica-based interlayer insulating layer may have an Si—H bond or an Si—R (R: alkyl group) bond. To form a silane-based monomolecular layer film, however, an Si—OH bond is required. If such an Si—OH bond is not present on the surface of the interlayer insulating layer, forming a silane-based monomolecular layer film is difficult. Another problem is how the surface of such an interlayer insulating layer should be processed. Yet another problem is in what way a monomolecular layer film of what type of structure should be formed on the surface of the processed silica-based interlayer insulating layer. Yet another problem is which material is suitable as a material for giving a catalyzing activity to the monomolecular layer film. Unless these problems are totally solved, it is impossible to provide a method of forming a semiconductor multilayer wiring board completely through a wet process from forming an interlayer insulating layer on a semiconductor substrate to embedding a wiring material in a wiring-layer forming space formed through a dual damascene process. As of now, such a method has not been provided yet.